1. Field of the Invention
The present invention relates to a master slice integrated circuit, and more specifically to an improved location of connection pads and input/output cells in the master slice integrated circuit.
2. Description of Related Art
Master slice integrated circuits have been constructed so that a number of circuit elements such as transistors, which constitute a number of logic circuits called "internal cells", are located in the form of a matrix at a center zone of an integrated circuit chip, and a number of circuit elements, which constitute a number of input/output circuits called "I/O cells" for interfacing between the internal cells and external circuits, are arranged to surround the zone of the internal cells. A number of connection pads are located at constant intervals at a periphery of the integrated circuit chip for interconnection between the I/O cells and lead terminals of a package. In general, a width of each of the I/O cells is made equal to a pitch of the pads.
In addition, a pair of power supply wiring conductors are located to pass over all the "I/O cells", so as to form two closed loops which surround the internal cell zone. The power supply wiring conductors are connected to the pads used for the power supply.
With recent improved performance of systems using the gate arrays, further increase of the integration density and the operation speed has become required. Because of the increase of the operation speed, the power consumption has increased, and the amount of electric current flowing through the power supply wiring conductors correspondingly increases. Accordingly, a voltage drop caused at a location remote from the power supply pad because of a wiring resistance of the power supply wiring conductors has become not negligible, and therefore, it has become necessary to increase the number of power supply pads provided on a single chip. This is more remarkable in the case that ECL logic circuits are formed.
In conventional integrated circuits, the power supply wiring conductors are connected to corresponding power supply pads through conductors which extending from the power supply pads to the power supply wiring conductors. As a result, a region of the I/O cell zone adjacent to each of the power supply pads cannot be used as an element formation region since there is no signal pad, and therefore, no circuit elements are formed in the region in question, so that the region in question is left as a wasteful empty region.
With the increased number of connection pins or terminals and the increased operation speed, when a plurality of connection terminals are simultaneously driven from a low level to a high level or vice versa, a large amount of electric current flows into or out from a ground level wiring conductor. Under this circumstance, in a terminal near to the terminal whose condition has changed from the low level to the high level or vice versa, the logic voltage level exceeds a threshold (which is a boundary level between the high level and the low level) for an instant, with the result that a malfunction occurs. Namely, this simultaneous driving gives a large adverse influence. As a countermeasure for this simultaneous driving, it is necessary to strengthen the power supply wiring conductors, and it has been known to locate the power supply pads adjacent to the terminals which are simultaneously driven. Because of this, an increased number of power supply pads have become necessary. In addition, an increased number of signal pads have also become required because of the increase of the integration density. These result in an increased size of chip.
On the other hand, in order to save the cost, it is necessary to make the chip size small. However, the miniaturization of the chip size is subjected to many restrictions such as a restriction attributable to an assembling operation including a wire bonding operation and a restriction due to the size of the I/O cells. In a recent technology, in the case of using a TAB (Tape Automated Bonding) process, the pitch of pads can be shortened to 80 .mu.m, but it rather becomes difficult to reduce the size of the I/O cells, because various functions have been required for the input/output circuits and because the current flowing through the I/O cells have become large. As a result, since the pitch of the pads is the same as the width of the I/O cells as mentioned hereinbefore, the size of the chip is determined by the width of the I/O cells.